ARM emulator (for PIC32)

[DarioG]

here it goes

Attachments:

ARMAcorn.C (25.5 KB)

[DarioG]

tested (!) and improved; support for both 26 and 32bit mode included
ARMAcorn.C (37.15 KB)

complete with test code:
ARMAcorn_PIC.zip (16.13 KB)

[DarioG]

Curious how... among the 5 emulators I made up recently, the "instruction cycle" lies always between 600 and 750nS (@200mhz). Which in turn means that "the powerful the emulated CPU, the better it performs".
Which makes some sense, I suppose. Especially since the underlying CPU is a 32bit itself.

[du00000001]

While I'd expect a target-specific emulation for 8-Bitters to run somewhat faster than a 16- or 32-Bit emulation, the overall result doesn't come unexpected: provided your decoding of the opcodes is efficient, the emulation itself might execute somewhat slower for CISC cores (as these tend to "do" more within a single op) than for RISC. So the 750 ns might stem from the 8051, the 500 ns from some RISC.
But basically, the emulation effort (on average) doesn't differ much between architectures.

[DarioG]

Yeah, and yeah makes sense

There's a loop, some outer switch(), then some further ifs or switch... and they happen for any opcode, be it a 8bit operation or 32; from 70 to 150+ instructions - of course just C without special tricks (for example, near-memory accesses or fine-optimized register allocation.

I can imagine that running the same code on a 8bit machine, things would be different. I want to try them on a PIC24 or dsPIC, just to see!

[DarioG]

Unoptimized 16bit CPU (dsPIC33CH) with XC16 (see other thread...) says that circa 1.2/1.5uS are needed per every emulated instruction (@180mhz)

Well, makes sense not bad. With optimization it may get down to a similar value to PIC32.

[du00000001]

dsPIC33CH would be running at a maximum of 90 MIPS @ 180 MHz (less, if massive branching is required - 90 MIPS only with highly linear code - not sure whether the lower limit would be 45 MIPS or more like 22.5 MIPS ).

So the performance of the 16-Bitter is not THAT bad.

[DarioG]

And, as I re-state, its assembler is MUCH better than MIPS

[DarioG]

Just as a matter of fact, an "hypotethical" dsPIC33FJ running @200mhz performs around 750nS/1uS per instruction (with optimization=1).
Considering the deep usage of bitfields which would benefit from BFEXT instructions, I suppose that, when the bug is corrected and optimizations are enabled, the dsPIC33C will do even better.